U.S. Pat. No. 4,866,741 describes a 3/2 frequency divider. The frequency divider comprises two D flip-flops. Each D flip-flop has a D input, a clock input, a Q output and a Q-not output. One flip-flop receives an input signal at its clock input, the other flip-flop receives the inverse of the input signal at its clock input. A logic circuit, which is in the form of an OR gate, is responsive to the Q-not output of each flip-flop. The logic circuit provides a low-state signal to the D input of each flip-flop when the Q-not output of at least one flip-flop provides a low-state signal. The logic circuit provides a high-state signal to the D input of each flip-flop when the Q-not output of each flip-flop provides a high-state signal. A further logic circuit, which is in the form of an AND circuit, is responsive to the Q output of each flip-flop and provides an output signal. The output signal has a frequency that is ⅔ times the frequency of the input signal.